1. Field of the Invention
The present invention relates to charge pump circuitry, including charge pump circuitry used in integrated circuits having multiple modes of operation.
2. Description of Related Art
Charge pumps are used in integrated circuit design to provide negative voltages, and positive voltages higher than a supply potential available to the integrated circuit. In some integrated circuits, more than one charge pump is required to serve different modes of operation on the integrated circuit, or to serve different circuit modules on the integrated circuit. The charge pumps on the integrated circuit are adapted for the particular mode of operation or circuit module so that performance of the charge pump meets the needs of the load being driven in such parameters as output voltage level, output current level and responsiveness.
For example, in integrated circuit devices including flash memory, a first charge pump can be used during a read mode and a second charge pump can be used during a program or erase mode. The charge pump used during the read mode maintains an output node coupled to word line drivers, which has a relatively high capacitive load, at a voltage (typically 4 to 5 volts) that is a relatively small increment higher than the supply potential, and must support fast response times. The charge pump used during the program or erase mode provides a relatively high voltage (typically 7 to 10 volts), which should be as uniform as possible in order to maintain uniform programming or erasing performance across the memory array.
Charge pumps are often implemented in multiple stages arranged in series, where each stage contributes an increment of voltage boost. Thus, higher voltage charge pumps often have a larger number of stages in series than lower-voltage charge pumps. Techniques have been investigated by which the series of stages in a multistage charge pump is configured to provide high voltage and low voltage modes, by selectively increasing or decreasing the number of stages in operation. Also, multistage charge pumps can be sensitive to changes in the supply potential, changes in the clock rates provided for driving the charge pumps, and changes in the load driven by the charge pumps. Thus, techniques have developed to compensate for such changes. Representative multistage charge pump technology is described in U.S. Pat. Nos. 5,781,473, 5,801,987, 6,486,728, and our own U.S. Pat. No. 6,573,780.
One prior art configuration of an integrated circuit with multiple modes is shown in FIG. 1. The integrated circuit in FIG. 1 includes a nonvolatile memory array 10 including a wordline decoder with a corresponding set of word line drivers in block 11, a column decoder 12 and a corresponding set of column select pass gates 13. A first charge pump 14 (read) is used during the read mode and a second charge pump 15 used during program and erase modes.
The output of the first charge pump 14 is coupled to a read regulator 15 and drives a wordline power supply node AVX which has significant load capacitance as represented by the capacitor symbol 17 on the node AVX. Leakage current allows the voltage on the load capacitance 17 to fall at a rate that changes with the temperature of the integrated circuit. The first charge pump 14 is driven by a four-phase clock 18, which is controlled by feedback through a read level detector 19. The four-phase clock 18 is controlled by a control logic block 20, which enables and disables the clock. The first charge pump is enabled in response to a “slow clock” 21 and by an address transition detection ATD system 22 that is responsive to input addresses. The “slow clock” 21 operates to periodically enable the first charge pump 14 during the intervals of low read activity, maintaining the voltage on the node AVX so that the integrated circuit quickly reacts to read events. The ATD system 22 is active during read events based on transitions in input addresses, and maintains the voltage on the node AVX at the desired read potential during periods of active use.
The output of the second charge pump 25 (program/erase) is coupled to a program/erase PGM/ERS mode regulator 26 and drives a bit line power supply node VPP during program and erase modes which is coupled through the column select pass gates 13 into the array during program or erase operations. The load capacitance driven by the second charge pump 25 is not illustrated in the figure. It is desirable however that the power supply node VPP have uniform voltage levels during program and erase operations, for more uniform program and erase results. Also, the power supply node VPP is typically driven at a higher voltage than the wordline power supply node AVX during read mode.
The second charge pump 25 is driven by a second four-phase clock 27, which is controlled by feedback through a program and erase level detector 28. The second charge pump 25 and second four-phase clock 27 are adapted for the program and erase modes, having a different number of charge pump stages operating at different clock frequencies as necessary to meet system specifications. The second charge pump is enabled in this example by a state machine 29 during execution of program and erase algorithms for the memory array 10. The state machine 29 is managed in response to a command decoder 30, typically responsive to data signals on the data bus 31, and other control signals applied to the chip.
As can be seen with reference to FIG. 1, prior art integrated circuits having more than one mode of operation, and requiring charge pumps for the multiple modes like flash memory devices, have typically required more than one charge pump circuit with supporting clocks and other logic. Charge pumps are relatively large circuits, with capacitors and other components that take space on the integrated circuit.
It is desirable to provide charge pump technology for multimode circuits, which conserves space on an integrated circuit, and improves efficiency of operation of the integrated circuit.